Samsung Develops Industry’s First 12-Layer 3D-TSV Chip Packaging Technology

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Samsung limited announced that it has developed the industry’s first 12-layer 3D-TSV (Through Silicon Via) technology.It has features which will help customers release next-generation, high-capacity products with higher performance capacity without having to change their system configuration designs.

This innovation is considered one of the most challenging packaging technologies for mass production of high-performance chips.It requires pinpoint accuracy to vertically interconnect 12 DRAM chips through a three-dimensional configuration of more than 60,000 TSV holes, each of which is one-twentieth the thickness of a single strand of human hair.

The thickness of the package (720㎛), High Bandwidth Memory-2 (HBM2) products, which is a substantial advancement in component design.

“Packaging technology that secures all of the intricacies of ultra-performance memory is becoming tremendously important, with the wide variety of new-age applications, such as artificial intelligence (AI) and High Power Computing (HPC),” said Hong-Joo Baek, executive vice president of TSP (Test & System Package) at Samsung Electronics.

“As Moore’s law scaling reaches its limit, the role of 3D-TSV technology is expected to become even more critical. We want to be at the forefront of this state-of-the-art chip packaging technology.”